Design And Study On The PLL Of Satellite Navigation Receiver Application

China has being working hard on constructing its own open global navigation satellite system independently. As the system being continually constructed and improved, the Navigation Satellite System will greatly push the developing of the National economic and society. The receiver terminal is a key part of the Satellite Navigation System, and the Phase-Locked Loop play a critical role in the receiver system.This thesis first stated the theory and the performance parameters of PLL, then calculated the Specification of the PLL demanded by the Navigation Receiver. The type I PLL's structure and linear model were presented. Derived type I PLL's transfer functions and calculated the loop parameters. Emphasized on studying the third order Charge Pump PLL, based on its linear model computed the transfer function and the loop parameter. The third order Charge Pump PLL's transient response such as phase step, frequency step and frequency slope were calculated. Utilized the second order approximate approach and nonlinear model derived the third order PLL's lock up and capture parameter. Stated PLL's simplified single side band noise model, estimated a set of PLL parameters as an example.After studied the PLL system and its noise model, the sub-module circuits of the PLL were designed. The Voltage Controlled Oscillator type, principle, and also the performance parameters were discussed. Then compared several VCO configuration, designed a quadrature VCO. Based on Studying the structure and the nonideal effects of the PFD-CP circuit, Designed a PFD-CP circuit which can suppress or eliminate several nonideal effects. Then the Loop Filter circuit has been designed. With the types and the requests of the divider circuit were stressed, an 80 divider ratio divider was designed.The Design of the PLL was based on TSMC 0.18 um process. Simulation results show that the Charge Pump Circuit's average current mismatch is 0.61%; the designed VCO achieved the phase noise of-94.64dBc/Hz at the 100 KHz offset frequency away from middle Frequency,and with a Figure of Merit of 177.6dB; the total average current dissipation of the PLL is 8.2mA,the lock-up time of the PLL is 4.5us.