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Design And Verification Of 1553B Protocol Processor

Posted on:2017-05-26Degree:MasterType:Thesis
Country:ChinaCandidate:P LiFull Text:PDF
GTID:2348330488474652Subject:Engineering
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The 1553 B bus is a two-way information transmission bus standard.It replaced the miscellaneous cables among computers,status monitor and other onboard equipment on the plane.It greatly improved the load capacity of an aircraft.This paper takes 1553 B as subject based on GJB289 A to design a 1553 B protocol processor.At first,the paper introduced the original of 1553 B and interpretate its technical features and performance advantages.Considering of the application internally and abroad,this paper predicts the future trend of 1553 B.Second,I study about MIL-STD-1553 B protocol including three transmission word format and the ways of message transmission.We build the overall structure and diverse function module in the way of top down design.After all,we translate all modules into Verilog code.The last step,we build the multiple Verification platform to simulate 1553 B RTL code in different environment.What's more,we use BFM to do Software and hardware co-verification.It makes the simulation more efficient and realistic.I accomplish the Digital front-end by design and verification.It has been taped-out through the hard work of other colleagues.Chip test proves the front-end word is successful.The features of the processor are: Protocol processor's powerful state machine transmit the massage automatically,generate interrupt and establish state information.A plurality of registers offers many programmable features and provide a wealth of information for the host.1553 B use the list message structure and provide message chain.It improves the utilization rate of memory by suppo RTing Variable size and relocatable data blocks.Bus command tables are linked form,if the command is block,it can skip the command block to next one and customize the interval between two messages.1553 B implements the message logging and time scale.Each sub address suppo RTs multiple(up to 128)message buffer and variable message length.We can configure the Watchdog time precision and error interrupts and clear Interrupt.After verification,the 1553 B designed maximum transmission rate can reach 10 Mbps with high reliability.All messaging features are in line with MIL-STD-1553 B standard requirements.
Keywords/Search Tags:1553B, Protocol Processor, Design, Verification, FSM
PDF Full Text Request
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