The IP Protocol Processor Based On FPGA

For the purpose of improving and optimizing the performances of the server in high-speed network circumstance, reducing terminal CPU's burden on Internet Protocols, TOE (TCP/IP Offload Engine) technology comes forth. TOE has greatly increased the efficiency of network terminals so that the bandwidth resources can be made the best use. At present some offloading chips have played an important role in network storage and high-grade servers.On the basis of analyzing deeply the fundamental principle of Internet Protocol, this paper adopts the design procedure of Field Programmable Gate Array (FPGA) to design the IP protocol processor. I frame the architecture of the IP protocol processor, and to plot out function modules of the system. According to the function of IP protocol, this paper divides the system into three main modules, including interface circuit module, sender module and receiving end module.After plotting out function modules, this paper uses Verilog HDL to contrive each module in behavior and set up test bench to simulate the protocol processor by Model Tech's simulation software ModelSim, then synthesize the behavior codes by Synplicity's synthesize tool Synplify Pro. The device I selected is Xilinx's Spartan-â…¡E XC2S300.I simulate the gate level codes that came forth after synthesizing by ADL's Active HDL6.1. Post-synthesis simulation indicates that the function of the protocol processor is correct.After succeeding in post-synthesis simulation, I place&route the protocol processor by Xilinx's integrated software ISE. Then the standard delay file is back-annotated into post-place&route simulation module to do the post-place&route simulation. Then timing analyzer and power analyzer integrated in ISE are used to analyze the frequency character and power character. The results indicate that the frequency of the protocol processor can attain 10MHz and the total power consummation is 128mW.At last, the BIT file is downloaded into the device through JTAG interface and the function of the device is verified by online logic analyzer ChipSocpe. The results of verification indicate that the IP protocol processor designed in this paper possesses the essential functions of IP protocol such as fragmenting, reassembly, routing and etc. and can process network data at the line-speed of 320Mbit/s.