Prototype Verification Of ARC Processor Interconnection Network Based On FPGA

As the performance of the chip becomes better and better with people's needs and Moore's Law,the chip design and architecture become more and more complex.Commonly used software verification has the advantages of flexible incentives and strong debuggability,and can intuitively feedback problems to design and verification engineers.However,in the face of large-scale and high-complexity processor system-level verification and shorter and shorter project cycles,software verification shows that the simulation time is too long and the real circuit cannot be accurately simulated.FPGA-based prototype verification can complement the shortcomings of software verification.It can quickly run tests on real FPGA circuits and shorten the project cycle.Successful verification can also greatly enhance engineers' confidence in products and projects.Based on this,take the project of participating in the prototype verification of a developing interconnection network of Synopsys' ARC processor as an example.By designing a synthesizable AXI transaction generation module,building the entire SOC system with other system components,building a prototype verification platform,developing proprietary test cases,and introducing the entire process of processor system-level prototype verification.The module to be tested in this article is the interconnection network of the processor,and its main function is to route and transmit various transaction access operations of the processor.A separate interconnection network cannot directly form a prototype on the FPGA.It must cooperate with the processor,AXI transaction generation module and external memory subsystems and other system components to form the entire SOC system.Among them,the AXI transaction generation module is designed to send AXI transactions to the device ports of the interconnection network as the main source of incentive transactions in the verification.The transaction generator adopts a top-down design method,which has the advantages of flexible configuration and controllable sending.After identifying and integrating these system components,EDA software and tools such as ARChitect,Protocompiler,and Vivado were used to generate FPGA prototypes.At the same time,according to the characteristics of this system,tests such as transaction checking,intensive sending of read and write transactions,and data copying in different storage locations have been developed to complete the verification of the relevant performance and functions of the interconnection network.The bandwidth and delay of the processor interconnection network module in the real circuit environment are tested on the basis of passing the basic read and write functions and concurrency capabilities of the processor.Under the 128 bit data width transmission test,the read transaction bandwidth of the interconnection network is14.22Gb/s,and the write transaction bandwidth is 15.06Gb/s.The delay performance of different ports on the interconnection network is also obtained,and the performance verification is completed.This set of prototype system environment can illustrate the function and performance of the processor interconnection network in a real FPGA circuit,and can accurately reflect the progress and status of the design and verification.In addition,ZeBu hardware acceleration simulation and VCS software simulation are used in this project,and the running time of FPGA is compared with them.In the article,the FPGA used only 0.78 s under the same test case running conditions under the same system construction,while the slowest VCS simulation takes as high as 3190.18 s just for the CPU time.The thousands of times the difference in running time can illustrate the speed advantage of FPGA prototype verification.This gap will eventually be reflected in the verification cycle and cost.