Research On Verification Techniques Of High-performance ESCA Co-processor

The increasing complexity of processor structure makes the efficient verification onthe performance of processor becoming increasingly important and critical. A highperformance multi-core processor-ESCA (Engineering and Scientific ComputingAccelerator) is designed to accelerate applications in engineering and scientific field basedon hybrid computing theory. ESCA Processor aims at accelerating computing intensivetasks in applications as a coprocessor. SIMD/Vector/Sub-word technology is used to gainhigh performance. This paper mainly focuses on the research and implementation of thekey verification techniques of accelerator ESCA.Firstly, this paper introduces its architecture from the point of the ESCA system,including computing array, control core, memory organization and bus interface etc. Then itexpounds the instruction set of ESCA processor which lays the foundation for betterunderstanding the verification objects, making verification plans as well as facilitating thesubsequent statement of mapping verification methods.Secondly, three verification methods including border value verification, equivalenceverification, and decision table verification methods are discussed and an integratedverification method is proposed. That is, based on whether there is a dependent relationbetween those input variables of the functional units to be tested, whether the single faultassumption is obeyed, and whether there exist a large amount of exception handling, theverification case set which is most accordant to the characteristic of the units under tested isgenerated by combing the baseline verification method and auxiliary verification method.Based on the above discussion, the software and hardware co-verification method isadopted to introduce the platform construction and workflow of chip functional verification.In addition, through the verification case generation of functional units such as IALU,FMAC and DMA, it shows the application process of the border value verification,equivalence verification, and decision table verification methods as well as the integratedverification method.Finally the selection case of integrated verification method on other functional units ofESCA is introduced as well as the adopted coverage tools, and the evaluation results ofESCA verification are shown considering both coverage rate and verification scale. ESCA processor design has been taped out with successful verification. It works at250MHz. Thechip area is17676582.00μm~2.