Design And Verification Of FPGA-based Network Protocol Processor

With the applications of embedded system constantly extends, embedded devices like handheld intelligent terminal access Internet becomes technology mainstream. The main problem of embedded Internet technologies is the high demand of the standard Internet protocol for memory capability and processing speed of computer, thus faster, more memory space and less power processor could be demanded. To solve this problem, we have to cut and transplant standard Internet protocol. Partial protocols can be realized in hardware so that lowers resource demand of the core processor to improve system performance and reduce system consumption. Thesis will introduce Ethernet MAC layer protocol and analyze format of data frames for MAC layer protocol and basic principle of CSMA/CD. How to design FPGA-based MAC layer protocol processor will be elaborated in the following chapter.When the chip designed become more complex, we should pay more attention to functional verification of hardware design. Currently, assertion-based verification technology has become an important method for functional verification, because of its high level of abstraction, powerful descriptive ability and able to locate errors, etc. So another important component of thesis is current hardware functional verification technologies, including formal-based static verification and simulation-based dynamic verification. Using assertion-based verification technology, how to design the dynamic functional verification platform of the Ethernet MAC layer protocol processor will be research. Finally, combined with the Ethernet MAC layer protocol processor designing, developing environment and verification tools of the system will be introduced and the function verification of traditional send/receive data and assertion verification program of the finite state machine will be given in this thesis.