Verification Platform Design For 1553B Bus Protocol Based On UVM

With the rapid development of the integrated circuit industry,the scale of integrated circuits continues to increase,the chip manufacturing process is constantly fine,and the deviation of complex hardware understanding may cause partial errors in the design function,resulting in failure of the entire SoC system,and re-spinning will cause additional economics.Loss,so the importance of verification work is obvious.The MIL-STD-1553 B bus was first proposed by the US military.It is mostly used in aerospace,aviation,and warships.However,its verification method often uses FPGA prototype verification or manual manual testbench method,which often consumes a lot of manpower and time.As a result,the chip still cannot be fully functional verified.The emergence of UVM(Universal Verification Methodology)has solved this problem.Its full validation,high efficiency,reusability and rapid positioning make UVM popular in academia and industry.Therefore,it is necessary to develop a UVM verification platform based on MIL-STD-1553 B bus.In this paper,the existing MIL-STD-1553 B bus BC(Bus Control)and RT(Remote Terminal)RTL-level design module as DUT(Design Under Test),the transaction level The SystemC model is used as a reference model.Analyze the verification function point of MIL-STD-1553 B bus,and give the method and design process of building UVM verification platform,including the component structure of the platform,the connection relationship between each component and the path of data transmission,and then collect the coverage result.Analyze its design flaws and vulnerabilities,perform regression testing after correction,continuously iterative design and verification work,and improve the completeness of verification by continuously increasing test cases and repeated regression tests.Finally,according to the function points of the verification plan one by one,the simulation waveforms of each function point are given,and the coverage results are collected continuously.After analyzing the reasons why the coverage rate is not increased,the design code and the test are continuously iterated according to the results.Incentives for regression testing,the final code coverage and functional coverage are 100%,to ensure the correct function of the BC and RT design modules,shorten the cycle of build verification environment on the basis of ensuring the correct and complete verification work,and effectively improve the verification efficiency.