Design Of Controller IP Core Applying To 1553B Bus Protocol

Originally, the MTL-STD-1553B bus was a standard bus of the American Integrated Avionics System, a medium for data and information exchange between different systems. Generally speaking, 1553 standard is similar to a communication protocol. 1553B bus is of high speed and flexibility, and it is also efficient in communication as well as easy to modify, extend and maintain.The 1553 bus protocol was designed for military use. As its merits kept being observed in practical use, however, China began to apply 1553B bus protocol to the design of civil airplane at the request of modernization and the upgrade of information system. Nevertheless, because 1553B bus protocol is highly complex and China is left behind in terms of technological advancement, almost all the 1553B protocols that are used in China are foreign protocol chips, of which the American DDC Company's were most frequently used.Based on 1553B standard and GJB289a-97, realizing MIL-STD-1553B protocol via FPGA is feasible. This paper elaborates method and procedure of designing 1553B via VHDL. For one thing it introduces method and procedure of designing modern digit system. Under this methodology and my understanding of 1553B bus protocol, we can design the system and compartmentalize the module. Then the paper describes the design of decoder, encoder, state machine and read-write controller. At last it discusses the simulation and synthesis of the design.This paper reveals the possibility of realizing a 1553B-processing IP core that is combinable, transferrable and upgradable basing on VHDL hardware depictive language. Where condition permits, it can be downloaded on FPGA and be realized as a product.