Design On Bus Controller IP Core Based On 1553B Bus Protocol

Aircraft Internal Time Division Command/Response Multiplex Data Bus(MIL-STD-1553B) is proposed to adapt to the needs of industrial and military. Since it hashigh reliability and flexibility, MIL-STD-1553B has been widely applied to military andindustrial fields, from large transports, space depot, bombers to all kinds of fighters, andmissile systems et al. As 1553B bus protocol processing chips are very expensive, it is ofimportance to research independently the design process of 1553B bus controller IP core forthe development of military technology and civilian industry.A kind of design method of bus controller (BC) IP core of 1553B is proposed based onstudying MIL-STD-1553B bus transport protocol. Integral design scheme of BC is given andthe design of each module is accompolished based on"from top to down"design ideas. Then,timing simulation results of main module and integral IP core are presented. Simulationsillustrate that BC can exactly accomplish the different transmission mode which is ruled by1553B protocol, and the design method is quite exact. The Verilog HDL hardware descriptionlanguage is used to compile program, and Quatrus II provided by Altera company is utilizedto compile, synthesize, and simulate the design process.