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Design Of 12-Bit Column-Parallel ADC For TDI CMOS Image Sensors

Posted on:2015-03-23Degree:MasterType:Thesis
Country:ChinaCandidate:T LvFull Text:PDF
GTID:2348330485493812Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Time-Delay-Integration(TDI) CMOS image sensor is a special type of line array image sensor. Under the condition of high scanning speed, the TDI image sensor can get higher signal-to-noise ratio and sensitivity compared with the traditional line array image sensor, so it is especially suitable for application in space imaging, medical imaging, industrial detection and so on. ADC plays an important role in the readout circuit of a TDI CMOS image sensor. There exist three ADC architectures utilized in CMOS image sensors: the chip-level ADC, the column-parallel ADC and the pixellevel ADC. The column-parallel ADC is the most widely used architecture because it provides a better tradeoff among readout speed, silicon area and power consumption. Therefore, this paper aims to design the column-parallel ADC for TDI CMOS image sensors.In this paper, firstly some ADC structures for CMOS image sensors are studied, and their characteristics are analyzed and compared. Then, a new two-step single-slope ADC is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. Then the proposed ADC architecture is implemented in a TDI CMOS image sensor as the 12-bit column-parallel ADC. Blocks such as the ramp generator, column circuitry and the readout circuit, are analyzed and designed. Finally, the layout is designed and submitted for fabrication.A prototype TDI CMOS image sensor with the proposed ADC architecture has been fabricated in a GSMC 0.18-?m 1P4 M CMOS process. The column ADC has average power consumption of 128?W, conversion time of 40?s and column width of 30?m. The measured SNDR and ENOB are 45.8d B and 7.3-bit. The chip size is 18.5mm × 11.9mm. The pixel array has 1024 × 32 pixels. The max line rate is 15.6k lines/s. Highquality images have been captured successfully by the TDI CMOS image sensor.
Keywords/Search Tags:TDI CMOS image sensor, column-parallel ADC, single-slope ADC, two-step single-slope ADC
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