Research On Readout Circuit Of Super Large Array CMOS Image Sensor

Resolution of Complementary Metal-Oxide Semiconductor(CMOS)image sensor is an important indicator.The higher the resolution,the more details can be discerned in the image.Therefore,super-large array CMOS image sensor has very important application value in aerospace,machine vision,medical imaging and other fields.With the improvement of CMOS sensor pixel array,the chip size is getting larger and larger,the length of the column bus and parasitic resistance are increasing rapidly,which leads to the increasing current voltage drop on the column bus,causing serious non-ideal effect.In this paper,theoretical analysis,mathematical modeling and circuit design optimization are carried out for the non-ideal factors of large array image sensor.In this paper,the pixel structure,Analog-to-Digital Converter(ADC)integration method and ADC structure of CMOS image sensor with super-large array are studied.The parasitic effect of column bus in signal transmission path is studied,and a static parasitic model of column bus is established.Using this model,non-ideal factors such as nonlinearity and dynamic swing reduction caused by parasitic effects are quantitatively analyzed,and a design optimization method for layout optimization is proposed.Large-size sensors need image sensor layout mosaic technology because they exceed the maximum size limit of the mask.According to the splicing requirement,the sensor architecture is designed,the readout module circuit is designed,and the analog domain correlation double sampling technology and misaligned storage technology are used to reduce the readout noise.The simulation results show that by layout optimization,the peak value of standard deviation under uniform illumination was reduced from 16.25 to 1.44,and Peak signal to noise ratio of image was increased from 58.0dB to 90.33 dB.In this paper,a 110 nm CMOS process is adopted.The width of each column is 6?m,the size is 2556?m *4265.101?m and the sampling period is 24.36?s.Differential nonlinearity reaches-0.0155LSB/0.0063 LSB,and integral nonlinearity reaches-18.70 LSB.Therefore,the layout optimization method can effectively reduce the non ideal factors of the column bus under the super large array.