Research On Integrated ADC Technology Of CMOS Image Sensor Readout Chip

Due to the benefit of low supply voltage, low power consumption and easy system integration with on-chip circuits, recent advances in CMOS image sensor have made them mainstream products, particularly in high-speed, high-resolution videography. High definition image sensor like4KX4K pixels have been reported. Currently, circuit area and power consumption is the major limitation, especially in portable products. The paper aims to study high precision and low power consumption Read Out Circuits (ROC) and the analog-to-digital converter (ADC) suitable for ROC.This paper presents the detailed analysis of the readout circuit architecture selection and analog-to-digital converter design principle for CMOS image sensor. Because of the simplicity, low power and good uniformity in column parallel architecture, this research focus on design of Column-Parallel Two-Step SSADCs. MATLAB modeling and analysis of a variety of non-ideal factors, meanwhile the process of specific design parameters calculation is showed. A14bits,70MHz Current-Steering DAC, which is used as Vramp Generator in Column-Parallel ADCs, and a design procedure for High resolution Current-Steering DAC, including calculation, is proposed as well.A Column-Parallel Two-Step SSADCs, which is implemented in a0.18-um standard CMOS process, is realized. The ADCs operates at a sampling frequency of100KHz. Simulation results shows that this Colum-Parallel ADCs achieve the ENOB of11.2bits and the power dissipation is256uW@VDD=1.8V.