Research And Design Of Column-parallel ADC Based On TDC For TDI-CIS

Time-Delay-Integration(TDI) CMOS image sensor is a special type of line array image sensor. Under the condition of high scanning speed, the TDI image sensor can get higher signal-to-noise ratio and sensitivity compared with the traditional line array image sensor, so it is especially suitable for application in space imaging, medical imaging, industrial detection and so on. As an important role in the readout circuit of a TDI CMOS image sensor, the design of ADC should meet the development trend of a large CMOS image sensor pixel array and fast imaging. There exist three ADC architectures utilized in CMOS image sensors: the chip-level ADC, the column-parallel ADC and the pixel-level ADC. The column-parallel ADC is the most widely used architecture because it provides a better tradeoff among readout speed, silicon area and power consumption. Therefore, this paper aims to design the column-parallel ADC for TDI CMOS image sensors.First and foremost, we compare several column ADC structures and propose a novel 10-bit single slope ADC based on two-step TDC technique. The process comprises two parts, the ATC and TDC. In former sector, slope generator is realized through the discharging from the capacitor to the current source, to guarantee the timing resolution of the slope, and the mismatch of comparator is eliminated by the three-stage cascade. And the latter one, realized in two-step quantization method, effectively reduces the area needed by applying a gate ring oscillator(GRO) and a counter, as well as offers higher resolution and speed by 4-bit vernier delay line(VDL). Additionally, we also propose a calibration circuit to mitigate the impact of propagation delay mismatch. Compared with conventional method, it adopts a simpler circuit without increasing quantization time or area in the fine quantization of TDC. Whereafter, we give the specific design of the modules, including slope generator, comparator, GRO, VDL and peripheral circuits. Finally, the layouts and the post simulation results of the proposed ADC are given.The proposed ADC is designed in 0.18 ?m CMOS process. The power dissipation of each column circuit is 232 ?W at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB(9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration applied on the TDC, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB respectively before calibration. The DNL and INL without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.