Research And Design Of Ramp Generator For Image Sensor Readout Circuit

In the era of rapid development of Internet of things and big data,image is one of the main ways for people to obtain information.As the main tool for converting Image signals into digital signals,Image Sensor ADC is widely used in security,medical,photography and other fields.How to accurately collect Image information is a challenging task.In this paper,a ramp generator for two-step SS ADC is designed.Based on 180nm CMOS technology,a ramp generator circuit is designed,which works under3.3V power supply voltage,has a conversion rate greater than 50KHz,a resolution of12bit and an input full swing of 1.2V.According to the structure of sensors,Image sensors mainly include two categories:Charge Coupled Device(CCD)Image Sensor and CMOS Image Sensor(CIS).Due to the gradual improvement of CMOS technology,CIS manufacturing cost is reduced and performance is improved,and it becomes the mainstream product of image sensor.The introduction of CIS readout circuit greatly reduces the CIS noise.Two-step singal-slope ADC(two-step SS ADC)can simultaneously achieve high resolution,small area and low power consumption in low-speed imaging,as an important module of the readout circuit,so it has been widely used in CMOS image sensor.In this paper,a Ramp Generator for the two-step SS ADC is designed.Based on the180nm CMOS process,a Ramp Generator circuit is designed to operate at 3.3V power supply voltage,with a conversion rate greater than 50KHz,a resolution of 12bit,and an input full swing of 1.2V.The paper compares the structure of three types of slope generator and decides to adopt the structure of resistance partial voltage slope generator.In order to optimize the overall area and conversion times,a two-step monobase slope generator is used.The noise,resistance mismatch,establishment time and establishment precision of the ramp generator are analyzed theoretically,and the design index is determined.Based on this,for the output buffer of fine slope generator,the paper adopts a structure of output buffer with constant common mode voltage to reduce the input misalignment voltage of output buffer.At the same time,the output signal of the ramp generator is designed to be output from the fixed port,which avoids the problem that the output impedance changes when the output signal changes,which is conducive to the establishment of the signal and the improvement of the linearity of the signal.Finally,the two-step singal slope generator is simulated by Hspice.The simulation results show that,at the clock frequency of 50KHz,the voltage gradient of the coarse slope generator is 37.5mV,which only needs 63.75ns to stabilize to 1/4LSB,and the voltage gradient of the fine slope generator is 293?V,which only needs 13.7ns to stabilize to 1/4LSB.In addition,the layout design of the two-step monocline slope generator was completed based on the 180nm CMOS process.The total area of the finished coarse slope generator was 314.7×118.3?m~2,and the total area of the fine slope generator was897.1×247.23?m~2.