| In today’s society, portable digital products have broad market and bright future because of its small volume, low power consumption, easy to carry. In the field of video technology, the CMOS image sensor has been widely applied because of its low power consumption, small size, compatible with other circuits and high integration. Because a high performance ADC(analog-to-digital converter) is the most important part of the image sensor, to design a high performance ADC under the standard CMOS process become urgent requirements.A 10 bit single-slope analog-to-digital converter(ADC) circuit based on Cadence is proposed.The key circuit includes the double sampling circuit, amplifier, comparator, ramp generator, etc. CDS double sampling circuit adopts the traditional double sampling circuit. Amplifier is designed with p-type folded-cascode operational amplifier. By making the switch S1 switch off ahead of switch S2 can effectively inhibit effect of charge injection and clock feedthrough, which can improve the linearity of ADC and signal to noise ratio. Comparator works at rate of 100 MHz. The whole comparator include pre-amplifier and latch comparator. In considering of the precision of the comparator, the output offset storage technology is adopted to improve the preamplifier offset.Ramp generator using the current steering wave generator. To realize the optimization of the circuit structure, a hybrid encoding method with 4 bit binary and 6 bit thermometer is applied to current source network.A 10 bits binary counter with reset function is designed by Verilog HDL. The layout of the ADC is completed with Calibre.ADC is designed using the UMC110 nm CMOS technology, the power supply voltage is 1.5V and all ADC circuits have been simulated with spectre simulator in Candence environment. Under the condition that the input signal frequency is 46.665 KHz and the sampling frequency is 95 KHz, the SNR and SFDR can reach 58.7 dB and 74.5 dB respectively, ENOB is measured to 9.46. |
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