The Research Of A High Resolution Column Parallel Single-slope ADC For CMOS Image Sensor

With the development of digital technology, the semiconductor manufacture technology, and the network, the CMOS image sensor becomes more and more attention-getting of the market. At present, the CMOS image sensor mainly develops to the high resolution, the high dynamic range, the high sensitivity, the ultra microminiaturization, the digitization, the multi-purpose direction. All of these bring more challenge to IC design especially to analog IC design. As a special interface connecting analog and digital circuits, high performance analog-to-digital converter is much more important in whole system design.For the requirement of high data throughput and high resolution of CMOS image sensor, this paper chooses column parallel single-slope ADC as an object to study, after analysis some ADC structure nowadays. Beginning with the principle of the column parallel single-slope ADC, the thesis analysis its function and characteristics, then parts system into digital-to-analog converter, sample/hold circuit, comparator, readout circuit, bandgap reference, and digital module. Based on all the study above, a real column parallel single-slope ADC circuit is designed.The major innovations of the paper are:(1) The column parallel ADC has high data throughput, which meets the requirement of the CMOS image sensor. The column parallel ADC also favors the expansion of the pixel array.(2) A sample/hold circuit is designed, which eliminates the FPN noise of the CMOS image sensor by double sampling.(3) The comparator uses the input offset storage technology, which realizes the high resolution while reducing the area and power consumption. The ADC is successfully taped out with 0.35um process, the testing result shows that, the presented ADC achieves a 8-bit resolution in 50Ms/s high speed, which is required by CMOS image sensor, while dissipating 9.5mW and costing 0.62mm2 area. The DNL and INL of the ADC are 0.8LSB and 1.1LSB respectively.