The Research And Design Of A High Speed Column Parallel ADC For CMOS Image Sensor System

In modern world, going with information exploding, people want to get information at any moment. So going with the development of the science and technology, pocket digital products will be in possession of the future market because they have advantages of small volume, low power and easy to take with. In the video applying field, CMOS image sensor has strongpoint of low power, small size, and high integration that it will substitute CCD sensor. The future developmental direction of CIS is large dynamic range, high resolution, ultra microminiaturization and multi-purpose direction. This makes a high request of design, especially with the development of the CMOS process, the design of analog circuit will be more difficult. ADC connects analog and digital worlds, is the important part of analog circuit. So it is so important that find some kinds of appropriate ADC for CMOS image sensor.This paper begins with the request of CIS, mostly discusses the characteristics and design method of the column-parallel ADC. Considering column-parallel ADC has good performance on the speed of handling data, the precision and the data throughput of ADC are the chief factor. In this paper, two kinds of ADCs have been expounded: Single-slope ADC and Cyclic ADC. In Single-slope ADC, its function and configuration, the implement of the ramp generator, the offset of comparator, the choice of low pass filter and readout circuit are depicted in detail. In Cyclic ADC, the theory explanation, configuration choice and circuit implement are explained roundly. Especially one way of elimination important noise of CIS——column FPN has been proposed, and this method lessens the image quality affection of column FPN in some degree and has a good effect.This design is based 0.18um process, and has successfully been simulated and validated. The single-slope ADC achieves 10-bit resolution in 50Ms/s high speed, while dissipating 10mW. The Cyclic ADC also achieves 10-bit resolution and it implements higher speed than single-slope ADC. It accomplishing one time of AD conversion only takes 2 us, so it makes the frame frequency six times more than the single-slope ADC but only dissipating 0.5mW. This advantage makes possible to improve the performance of CIS. In a word, two kinds of ADC have advantages of themselves, and they are two important column parallel ADC.