Dynamically Reconfigurable Design Ofuniversal Bus Based On FPGA

With the rapid development of micro-electronics technology, modern testing system is developing in the direction of general system.Therefore,testing system must have a series of advantages,such as general design?extension and so on.Bus is an important part of the testing system.Aiming at this research hotpot,this thesis develops a dynamically reconfigurable system of universal bus based on FPGA,which is used to switch several bus communication modules in real time.Firstly,this thesis analyses the domestic and overseas research status of testing system of data communication bus.According to the development of general direction,the overall design of testing system of data communication bus is given.Then monitoring interface on the PC is designed and interface circuits of corresponding buses are added outside.By means of analyzing communication protocol of different bus,several communication modules are designed with the programmable feature of FPGA including ARINC 429?RS232?RS422?CAN bus and so on.The function of every module is simulated and the waveforms are analysed in detail.Afterwards, combining the dynamically partial reconfigurable method based on EAPR and embedded development process based on FPGA,dynamically partial reconfigurable region is planned manually in the chip of FPGA,which is used to design a bus communication system that is reconfigurable.The design and implement of this system are analysed in detail from several respects of the design of hardware processor system?application software and dynamically partial reconfiguration.By combining interface on the PC?micro-processor embedded in the FPGA with internal configuration access port,the system can load different bus communication module from an CF card outside in real time,which indicates that small scale hardware is able to achieve the function of large scale system.Finally,the function is verified on the development board of FEM025.The result of the test indicates that the system designed in this thesis meets all the engineering requirements.The interface is friendly and easy to operate,which has high utility value.