Design And Development Of Partial Dynamic Reconfigurable Systems

With the development of information society, more requirements are proposed to the modern electronic products, while the traditional calculation methods show their limitation gradually. The field programmable gate array promotes the development of reconfigurable technology. The dynamic reconfigurable system designed with FPGA can perform complex circuit functions using as few resources as possible. It also has characteristics such as short development cycle, good application flexibility and high performance, which have brought a lot of researchers’attention. Specifically, reconfigurable technology is a new design method of modern digital circuits, and has become a research focus for both national and international scholars.In this paper we focus on the design flow and the scheduling algorithm of partial dynamic reconfigurable microprocessor systems. We also create a specific implementation plan, furthermore demonstrate the plan with experimental verification and analysis. The main work includes:in-depth study of internal structure of the FPGA and its reconstruction theory, analyzing and comparing the existing design methods of the dynamic reconfigurable system, and adopting a design process for the dynamic reconfigurable system based on early access partial reconfiguration. The design of the partial dynamic reconfigurable system is completed with development tools ISE, EDK, PlanAhead and ModelSim. We demonstrate that the system achieves reconstruction of digital modulation of ASK, FSK, PSK through using embedded microprocessor PowerPC to control the reconstruction process. Then, the design is downloaded on the Xilinx ML403development board. Resource utilization and reconfiguration time of the system are analyzed. Because dynamic reconfigurable system has two computing resources, CPU and FPGA, system operations are designed as a hybrid task that combines both software and hardware executions, which results in a hybrid task scheduling algorithm. The algorithm uses a single CPU system model with only one configuration port. The reconfigurable resources are divided into several identical regions. Hardware task is divided into configuration phase and execution phase, which can be placed in any region. By calculating and comparing the earliest ending time of needed executing on software and hardware, algorithm will execute the task on CPU properly. Finally through experimental comparison algorithm, both scheduling success rate and run time are greatly improved.