Implementation And Optimization Of High Reliable System Design Based On Partial Reconfigurable FPGA

With the highly developed Semiconductor technology, the scale of the hardwarelogic resources on the SRAM based FPGA was increased, so the high dependabilitysystem of FPGA is necessary. Triple Modular Redundancy (TMR) technique is acommon structure using three duplications of original circuit and a majority votermechanism to implement the high fault tolerant ability, which provides system the highreliability, but due to the required of a large numbers of extra hardware logic resourcesfor the implementation, the TMR method will suffers from the area overhead problem.Partial reconfiguration technique is an advanced technology that can reconfigure aportion of a FPGA while the other part won’t be affected. By applying the partialreconfiguration technique into a common TMR structure, it can improve the areaefficiency of the system. However, this method will bring the time overhead due to thereconfiguration time.To deal with the time overhead problem, an optimized configuration look-aheadpartial reconfiguration TMR structure has been proposed, which use an additionalreconfigurable partition to configure the next reconfigurable module while the currentreconfigurable module is working in the first reconfigurable partition. The result ofexperiment shows that the proposed partial reconfiguration TMR structure withreconfiguration look-ahead mechanism can reduce the area utilization compare totraditional TMR structure and optimize the time overhead problem invoked by partialreconfiguration technique.