Research On Dynamically Reconfigurable Cache For Embedded Microprocessors

As CMOS technology continues to scale down, microprocessors suffer more from the energy consumption problems. Nowadays, the energy consumption has become a major constraint in the state-of-art embedded microprocessors design. Caches are widely employed in modern microprocessor design to bridge the increasing speed gap between the processor and the off-chip main memory. Consequently, caches comsume a significant amount of the transistor budget and chip die area in microprocessors, and also the energy budget. Thus, the caches deserve a complete study of its energy behavior for the next generation microprocessors.The demands for cache vary significantly from application to application and even within the different phases of a given application. Traditional cache has fixed architecture, which may not fit certain application. This thesis studies the dynamically reconfigurable cache architecture. The cache monitors and reacts to the phase changes in application, and dynamically adapts its architecture to meet the application's requirement. The evaluation results show that the dynamically reconfigurable cache can achieve a significant energy savings with minimal performance degradations. The following is the main contributions:1. The On-line Cache Resizing (OCR) techniques are proposed. The OCR observes the application execution behavior, and dynamically enable/disable particular cache ways to make cache effective size changeable. First, a novel cache architecture which supports size change is analysed. Second, an execution monitoring mechanism employs additional tag array to observe the miss rate for each cache size. Finally, an architectural cache energy model is established. A reconfiguration algorithm is developed to evaluate each cache size and finally determine the optimal one.2. The Reconfigurable-Associativity Cache (RAC) techniques are proposed. Whenever an application phase change is detected, the RAC triggers an associativity exploration behavior and sesearches the best one for current application. First, we analyse the associativity's impact on cache performance and energy consumption and discuss the way concatenation cache architecture. Second, an arbitration mechanism is developed to monitoring the application runtime behavior. Whenever there is a phase change, the mechanism explores each associativity candidate and determines the optimal one. Finally, an adaptive threshold strategy is studied, which makes the arbitration mechanism much more effective.3. The Reconfigurable-Size/Associativity Cache (RSAC) techniques are proposed after combining the previous OCR and RAC. RSAC dynamically reconfigures both cache size and associativiy, which makes the reconfiguration space much larger. First, we describe the RSAC architecture and discuss the hardware implementation. Second, an efficient reconfiguration strategy is developed. Since the design space becomes larger, the efficiency of candidate cache exploration is important. A smart reconfiguration strategy can achieve a significant reduction in both hardware and energy overhead.