The Fault-Toleranc On FPGA Of Dynamic Partial Reconfigurable

Based on its reconfigurable characteristics, FPGA can be used to develop high stability and safety electronic products in a fairly short period of time. The dynamic partial reconfigurable characteristics of FPGA are used to realize the fault-tolerant systems. This application not only improves product efficiency, simplifies software design, shortens development cycle, and makes the system safer and more reliable; but also can ensure the complex logic hardware stability and reorganization.In this paper, we focus on utilizing the reconfigurable technology based on FPGA to design fault-tolerant systems. Main contents include:In-depth study of the FPGA principle and the design process, exploring design method of dynamic reconfigurable system, and proposing an improved design method of dynamic self-reconfiguration system.Using EAPR’s principle and design methodology, the original design process is simplified based on existing logical dynamic reconfiguration. Subsequently, it achieves dynamic partial reconfiguration. The proposed design method is applied to fault tolerant system using Xilinx development tools and FPGA development board as the development platform. Through dynamic reconfiguration of the simulation error function, a reliable and dynamic partial reconfiguration modular design is established. An example is given to demonstrate the feasibility and efficiency of the design method.A preliminary study is done on the effect of fault recovery ability of dynamic partial reconfiguration on fault tolerant system. Using dynamic partial reconfiguration system in the process of implementing dynamic partial reconfiguration, works have been done to establish the initial design platform. The static and reconstruction of the regional setting module have been divided. Conduct parallel design of each module, and then solve communication problems between the reconstruction module and reconfigurable module, or the reconstruction module and static module and design constraints. After all generate bit stream files and combine assembly. To complete the whole system, the same method is also used to recover errors and simplify the recovery process, which results faster recover process speed. At the same time, we propose a central control system of embedded microprocessor with embedded chips hard-core processor, to manage and schedule other logical resource on the chip. Some techniques about communicate on developing the FPGA reconstruction system and improving reconstruction time are also discussed in the paper.