A Study On Hardware Framework And Development Method Of Dynamic Partial Reconfiguration

FPGA-based reconfigurable technology, which can achieve another different circuit function through recongfigurating FPGA internal logic resources, has both the flexibility of general-purpose processor and the high-performance of ASIC, and becomes a new option for calculation method. Especially, the partially reconfigurable technology, which can reconstruct a new computing platforms through dynamically reconfigurating FPGA's partial logic resources, grately increases the utilization rate of FPGA and the efficiency of reconfigurable system, and is becoming the hotspot in computer architecture research in recent years.At present, dynamical partially reconfigurable technology is still in academic research and performance verification phases. A lot of important technologies have to be resolved. For example: the lack of universal reconfigurable hardware architecture, the problem of how to shorten the reconfiguration time. However, dynamical partially reconfigurable technology has shown great superiority, such as the system's real-time processing capabilities, adaptive capacity, fault-tolerance, lower power consumption, which has great significance theoretical research and practical application. This paper studies on these issues and mainly completes the following tasks:(1) Because Xilinx's Virtex series FPGA devices is used for the research platform in this paper, we analyze the structure of SRAM-based FPGA, the recofiguraion mechanism, and the process of configuration. The paper also analyses the method of reconfiguration. The EAPR design methodology which supports two-dimensional region reconfiguation is used to achieve FPGA dynamic partial reconfiguration, through which the FPGA function is divided into several modules, and each module possesses separate physical area in FPGA. These modules can be reconfigured when other modules operate normally. The paper also analyses the difference-based and bitstream-based reconfiguration method.(2) This paper also presents a new dynamic self-reconfigurable hardware platform based on Virtex series FPGA which supports dynamical partial reconfiguration, which is used for testing the performance of the reconfiguration computing and operating system migration. Powerpc processor is used in this platform as a configuration controller, which is used to control the process of dymanic reconfiguration. Compared to the way of external control mode, self-reconfigurable mode of reconfiguration has significantly faster reconfiguration speed. Besides, this paper also analyses the component of the platform.(3) Finally, this paper also does a research on reconfiguration time, which has a direct relationship with the size of reconfigurable module and the speed of data configuration during reconfiguration process. Virtex-4 FPGA, propsed in this paper, supports two-dimensional region partial reconfiguration which allows reconfigurable module as an arbitrary rectangle. Compared to VirtexⅡwhich only supports one-dimensional partial reconfiguration, the scale of the reconfigurable module in virtex-4 will be greatly reduced and reconfiguration time will be also significantly reduced. Besides, the new reconfigurable hardware architecture presented in this paper, used the internal configuration access port (ICAP) which adopts parallel mode for data transmission. Compared to JTAG configuration mode, both the data transmission frequency and bandwidth are significantly increased. Therefore, the configuration speed is greatly increased, and configuration time is significantly reduced.The fruit of this paper establishes a firm foundation for mobile communication networks, fault-tolerant technology, and electronic systems in aerospace. It also affords a good reference for reconfiguraiton computing based on FPGA.