Design Of 8T SRAM At Near Threshold Region

As technology scales, and the increasing of chip integration, SRAM arrays occupy a large area of chips in the state of the art microprocessors and System on Chips(SOC), so its power consumption has been a major problem. What’s more, when device size below 65 nm, process variation has great impact on circuit performance.By reducing the supply voltage to the near-threshold region to reduce the power consumption with a 65 nm technology, which near-threshold voltage is 0.5V. However, when operating in this region, the performance of 6T-SRAM is very poor, and more sensitive to the process variation. In this paper, we introduce a novel 8T-SRAM, when compared to the standard 6T-SRAM, they have the equal static power consumption, and its read noise margin has doubled. So this 8T-SRAM not only has low power consumption, but also has high stability. Further, the impact of process variation on the read noise margin has been analyzed, when compared to 6T-SRAM, 8T-SRAM is not sensitive to process variation.The 32×8 bits SRAM is designed with the novel 8T-SRAM, consisting with cell arrays, address decoder circuit, sense amplifier, column selecting circuits, etc. NanoSim simulation shows that the whole circuit can operate in the near-threshold region, with a static power consumption of 1.54μW, and its working frequency can be reached 50 MHz. The area of one SRAM cell is 2.2μm×2.58μm, and the area of the memory array is 37.5μm × 91.75μm. As a result, the proposed 8T-SRAM can be operated in the near-threshold voltage with low power consumption and good access performance.