1.2um EEPROM Low Voltage Failure Analysis And Process Optimization

As the portable electronic products are developing rapidly, low power consumption EEPROM design has been a popular field. In this paper, a product fabricated by the mature technology of 1.2um EEPROM process is introduced. To achieve the target of low power consumption, the designer modified the circuit's layout. However, the pilot wafers made by the primary process failed severely under low voltage testing condition.Firstly, we collected and analyzed a mass of PVM data to investigate the root cause of low voltage failure. Then, the circuit's failure mechanism was discussed theoretically. We studied the theories including the influence of floating-gate to EEPROM memory cells, the relationship between erase/write characteristics and Fowler-Nordheim tunneling mechanism, the working principle of the charge pump in a high voltage generator, the influence of key process parameters to the circuit, the relationship between failure and threshold voltage of POLY1 NMOS, and so on. Following the above analysis, we proposed a solution to solve the problem by optimizing some process parameter.To modify the process parameter, we did numerous process and device simulation with the TCAD software. On the basis of the simulation results, some splits were arranged correctly and the appropriate optimizing condition and control limits were found. Finally, we changed the process parameter of VT implant dose and enhance the yield 15 percent in a short period of time successfully, meeting the customer's requirements. Then, around 18,000 pieces of wafers were produced quickly and brought considerable economic benefits to the corporation.