Research And Design Of SRAM Circuit Applied To Ultra-low Voltage System

As an important part of SoC,SRAM has been widely used in high-performance systems such as computers,portable mobile devices,automotive electronics,sensors,and medical devices that require fast access.With the continuous progress of the semiconductor manufacturing process,the number of transistors integrated on the chip has increased exponentially,but it has also led to an increase in power consumption.The power consumption of an SoC affects the life of a battery-powered product.In order to reduce the power consumption of the SoC,it is of great research significance to design the low power consumption of the SRAM which accounts for a large proportion of the SoC area.The most effective way to reduce power consumption is to reduce the supply voltage,which can reduce the dynamic power consumption in a quadratic form and greatly reduce the static power consumption.However,when the supply voltage scales to the near or subthreshold region,the stability of the cell is weakened due to the influence of process parameter fluctuations,and it may not even work properly.In addition,the soft error rate is significantly increased at low voltages.The bit-interleaved structure combined with traditional error correction code(ECC)can effectively eliminate soft errors,but it will cause a half-select disturb that affects the stability of the half-selected cells.Therefore,the SRAM design applied to ultra-low voltage systems faces a series of challenges.In response to the above challenges,this thesis designs a SRAM cell that can be applied to ultra-low voltage systems,it can work stably under low voltage to reduce the system power consumption.This thesis firstly made a comprehensive review of ultra-low voltage SRAM design.The low-voltage SRAM designs in the past ten years are analyzed and summarized,which provides a reference for the future low-voltage SRAM design.The content of the review covers the various parameter of the low-voltage SRAM design,the induction and classification of the techniques that improve the cell stability,the solution of the read bit-line leakage problem,the soft errors issue and the solution of half-select disturb as well as the introduction of various peripheral auxiliary technologies.Under the guidance of the review,we propose a 10 T SRAM cell for ultra-low voltage systems.This cell can be applied to the bit-interleaved structure to solve the half-select disturb.The proposed cell and several other low-voltage SRAM cells were simulated and compared under a 40-nm standard CMOS process.The simulated parameters include hold static noise margin,read static noise margin,write margin,read and write power consumption,static power consumption and minimum operation voltage.Simulation results demonstrate that the proposed 10 T SRAM shows higher read stabilty and write ability under low voltages.At a 0.5V supply voltage,the RSNM of the proposed 10 T SRAM cell is equivalent to that of the conventional low-voltage 8T cell,and its WM is 6.14 times that of the 8T cell.Considering the 3? failure probability,the Monte Carlo simulation was performed at the worst process.The minimum operation voltage of the proposed 10 T cell was measured to be 0.438 V.Finally,we design a 1Kb SRAM array and the corresponding peripheral circuits for the proposed 10 T SRAM cell.The simulation results showns that at TT corner,0.438 V and 25 °C,the maximum operating frequency of the cell can reach 20.4MHz,the read power consumption is 1.26?W,the write power consumption is 2.45?W,the static power consumption is 0.37?W,and one write and one read energy consumption is 0.284 pJ.