Research On Efficient Threshold Voltage Detector Algorithm For Multi-level-cell NAND Flash Memory

Due to its high storage capacity,fast read speed,low cost and cost-effective performance,multi-level-cell(MLC)flash memory has replaced mechanical hard drives as dominant choice for data storage,from the various consumer electronic products to enterprise data centers.However,as the process scaling and the multi-level cell technology,the high-density flash memory suffers from severer noise such that its performance will be dramatically deteriorated,thereby greatly reducing the reliability of data storage.To further enhance the reliability of flash-memory data storage and extend the lifetime,the state-of-the-art signal detection algorithms and low-density parity-check(LDPC)codes with soft-decision decoding have been adopted in solid-state data storage controllers.However,in multi-level-cell flash-memory channel,the accuracy of threshold voltage detection is directly dependent on the read reference voltage,which makes the estimation of the read reference voltage particularly important for improving the reliability of data storage.Moreover,the latency problem associated with channel threshold voltage detection requires further study.Combined with the threshold voltage distribution characteristics of the multi-levelcell NAND flash memory channel,this paper mainly studies the dynamic threshold voltage efficient detection algorithm.Furthermore,by constructing flash-memory channel detection and LDPC error control coding simulation environment,this paper analyzes the performance of threshold voltage detection algorithm.Finally,further research on the latency problem is given.The specific research contents and innovations are summarized as follows:(1)This paper deeply studies the structural characterization of NAND flash memory,programming and erase mechanism and various noises.Then,by establishing a multi-level flash channel model,the influence of various flash noise on threshold voltage is analyzed.(2)The basic principle of LDPC codes and various decoding algorithms are studied,Then,LDPC codes is applied to NAND flash memory,and the reliability of flash memory is analyzed.(3)The state-of-the-art threshold voltage detection techniques and their application scenarios are analyzed in detail.Then,an efficient cell-state-distribution-assisted threshold voltage detector is proposed.Moreover,the proposed CSD-TVD scheme does not need to estimate the probability density function of the threshold voltage in advance,and has better performance.(4)According to the retention characteristics,a higher programmed state shifts faster than a lower programmed state as the retention age increases,a low-latency LLCSD-TVD scheme is proposed.Moreover,based on the concave function distribution of error bits in the overlap region,an improved ROR scheme is proposed to effectively reduce the number of read operations,which uses non-uniform read-retry mechanism.