Researches And Designs Of Logic Cell In Low-Voltage

Nowadays, portable devices are more attractive to its function of communication and multimedia; therefore, the power demand is increased but the power budget is limited by the battery technology. The most effective mean to reduce the power consumption is lowering the supply voltage directly. However, circuits with lower supply voltage are easier to be affected, which leads to errors. What’s more, continuously lowering the supply voltage would lead to overmuch circuit performance sacrifices. Near-Threshold-Voltage (NTV) has been announced as a low-power design concept setting the supply voltage closing to threshold voltage of transistors to pursue maximum energy efficiency without sacrificing excessive circuit performance.In this thesis, we applied a probabilistic-based approach based on common decision theory to deal with noise issues in nano-scale computing circuits. At the same time, noise sources are isolated by the virtual VDD and GND. The proposed design rule has lower cost and achieves great noise-tolerance in the environment which has multi noise sources. We apply the design rule to a 16-bit carry look-ahead adder. In TSMC 90nm CMOS process,1.2V supply voltage, the proposed design can perform higher noise immunity. The SNR of output signals is always about 20 dB.To achieve the highest energy-efficiency, we decrease the supply voltage to the region near the threshold voltage of CMOS. In this thesis, a new mirror adder with different type body bias is introduced. This adder applies forward body bias (FBB) in its carry part and zero body bias (ZBB) in its sum part, which achieves higher speed and higher energy efficiency.A high energy efficiency hybrid NTV adder design with output conditional feedback controlled keeper was proposed in this thesis. We combined static logics together with dynamic logics to achieve better driving ability and higher speed. Moreover, the conditional feedback controlled keeper mitigated the signal contention in evaluation phase under NTV, power consumption and delay was also reduced. The energy efficiency of proposed hybrid 32-bit adder can be enhanced by 114% as compared with prior-art design under 0.4V; also the process variation tolerance was improved.