Research Of Process Variations Of Gate All Around Field Effect Transistor (GAAFET) And Its Impact On Performance Of SRAM

The semiconductor industry has been developing rapidly,and great progress has been made in circuit design,transistor,and manufacturing processes.The core device widely used in the current integrated circuit industry is FinFET,but as the technology node will enter 5 nm or even below 3 nm,FinFET could not achieve faster switching speeds and lower power consumption.Gate All Around Field Effect Transistor(GAAFET)is considered as the best replacement for FinFET devices because of its better gate control ability,better switching characteristics and more effective suppression of short-channel effects.However,the process of GAAFET channel structure is very complicated,and random fluctuation of the process is very obvious for device at small sizes.The impact of the process fluctuation on the electrical performance of the device needs special attention.In response to the GAAFET process fluctuations and its impact on SRAM performance,the research content and research results of this paper are as follows:GAAFET device structure at 5nm technology node was built with the help of TCAD tools.The characteristics of the device like shape,structure size and doping concentration were studied and analyzed.The electrical parameters of the DC characteristics of the device were extracted through TCAD simulation.The fluctuation simulation is performed based on the GAAFET device structure.Random Doping Fluctuations(RDF),Interface Trap Fluctuations(ITF),Metal Work Function Variation(WFV),and Oxide Thickness Variation(TOX)are introduced into GAAFET for simulation.The sample number of single simulation is 500.The effect of Mechanism and correlation is studied by different device fluctuations,and the fluctuations of electrical parameters of the effects of different fluctuation mechanisms are analyzed by comparing the results.For the GAAFET selected in this thesis,the threshold voltage variation caused by the fluctuation of WFV is the most obvious,the standard deviation of work function is 19.2mV,and the effects of trap fluctuation and work function variation will promote each other and need to be considered simultaneously.The SRAM memory cell built by GAAFET device is researched in this thesis.The simulation of its read data state,write data state and hold data state is performed by constructing 6T-SRAM memory cell.Combined with the GAAFET process variation,the change of static noise margin when different devices fluctuate is extracted,the antiinterference ability of the memory cell is analyzed carefully.Because the change of the threshold voltage directly affects the static noise margin,the work function variation has the most significant effect on the reduction of the noise margin of the memory cell.WFV reduces the average read static noise margin by 11 mV,and the standard deviation is 15 mV.In the structure of the 6T-SRAM memory cell,compared with the pull-up transistor and pull-down transistor,the fluctuation of electrical parameters of the access transistor has a greater impact on the static noise margin of SRAM.Considering the power consumption optimization of the memory cell,a comprehensive analysis of the impact of reducing the supply voltage of the memory cell from the perspectives of its read capability,write capability,leakage power consumption,and static noise margin was investigated.Comprehensive evaluation to improve the antiinterference ability and power consumption of SRAM.The work of this thesis has great guiding significance to optimize the structure design of GAAFET devices of nanometer technology,and to analyze the influence of different device process fluctuations and the stability of SRAM memory cells.