Research And Design Of An Programmable CMOS Integrated Charge Pump Phase-locked Loop

Charge pump phase-locked loop(CPPLL) design is used in the modern system of circuit design more frequently. Its excellent properties,such as low power consumption, low jitter and the larger frequency range of capture,are favored by the design engineers.At the beginning of this article, the development history of phase-locked loop is introduced, the development history of PLL can be a reference for the theoretical research in the future. Then this article studies basic theory of charge pump phase-locked loop systematically. It introduces the structure and mathematical model of phase-locked loop, it can be used to produce relatively stable clock. And the article also fully describes performance of the phase-locked loop system and each module of the phase-locked loop.This paper describes a kind of CPPLL structure that the current is programmable. Most of the modules of phase-locked loop is improved and optimized at the basic structure of PLL,especially,the PFD module and the CP module are improved in structures. The PFD is designed with the structure which is similar to real single phase D flip-flop. And the CP is designed with the structure of the charging current compensation. 0.18?m CMOS technology and 1.8V power supply voltage standard are used in the design. All circuit elements are made of MOS devices completely in the circuit design. The results of the simulation which is obtained from the Spectre component of Cadence software. The performance of each module of the PLL is simulated firstly, and then the performance of PLL system is simulated. From the results of the simulation, the speed of PFD is improved and eliminates the phase "dead zones" in this design;the faster speed of CP charging leads the clock to be locked quickly, the performance of the phase-locked loop reaches the requirements of the technical standards.