The Built-in Parameter Measurement Circuit For Phase-Locked Loop

The Phase-Locked loop (PLL) is an essential block of high-speed communication system and SoC (system on chip). With the growing popularity of PLLs, the need for testing PLLs is improving. But conventional PLL tests are expensive, inaccurately and there are some liminations on test equiments. Built-in self-test (BIST) is an effective solution to solve these questions. The key performance metric for PLLs is often stated in terms of jitter. The built-in jitter measurement (BUM) is the main issue for PLL testing and becomes a research highlights.This thesis firstly summaries PLLs, jitter and BUM. The design goal is proposed of all digital BUM circuit with good accuracy. Then the issues of the classics undersampling BUM method are analyzed, including the strict demands on undersampling clock, measurement inaccuracy and large area overhead. The central symmetry undersampling BUM scheme is presented towards these problems. This scheme is made of mutual undersampling, central symmetry and predictability jitter measurement technology.1) Mutual undersampling method calculate the jitter of each PLL through mutual measurement.2) Central symmetry technique includes an improved way of jitter extraction, which filters other jitter component to measure the cycle-to-cycle jitter and symmetric abandon method adding up a probability density function histogram with evaluating the jitter absolute value.3) The final result is obtained by the best measurement ratio or prediction of predictability jitter measurement technology, which needs a variety of measurements by different resolutions.A mixed experimental model is built in MATLAB according to the proposed method. Experiment results show that resolution is linear correlation with measurement value (correlation coefficient is-0.985) and mutual undersampling measurement value is influenced by jitter of both under-test PLL and reference PLL. Then the presented BUM circuit is fabricated on the SMIC 40nm technology by standard digital circuit design flow, whoes layout area is 4434.6μm2 (8.8% of the PLL area). Pre-simulation is done to verify the function of the circuit. Post-simulation shows that the measurement error is 1.92%. At last, the measurement error is 3.9ps through the DE2-115 FPGA board of Altera.