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Research And Design Of High Precision Phase Locked Loop Jitter Measurement Circuit

Posted on:2019-10-26Degree:MasterType:Thesis
Country:ChinaCandidate:M Y DaiFull Text:PDF
GTID:2428330566995959Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Phase Locked Loop(PLL)is an indispensable basic circuit in analog and digital communication systems.PLL measurement techniques based on Built-in self-test(BIST)have emerged.Jitter is the most important clock parameter of on-chip clock.In various circuit characteristics,jitter measurement is the most effective method to evaluate clock characteristics.High-precision jitter measurement circuit has become the central issue in PLL testing field.In this thesis,we present a jitter extraction technique based on edge alignment,which is based on the low accuracy and large measurement error of the existing jitter extraction methods for undersampling circuits.The jitter extraction technique based on edge alignment is used to realize high-precision jitter measurement target.Simultaneously,for solving the problem of the single component measurement,the idea of edge alignment is applied to the measurement of periodic jitter and long-period jitter.A high-precision jitter measurement circuit is proposed.In the periodic jitter measurement mode,the circuit aligns the unstable transition regions in the sampled output signal according to their edge bits to obtain the jitter value of the periodic jitter of the measured signal.In the long-period jitter measurement mode,the application of an interpolation sampler increases the sampling point to increase the sampling rate,and the measurement counter provides a fixed period.The edge of the unstable transition region in the sampled output signal is aligned and analyzed with the edge of the fixed period signal to obtain the jitter value of the long-period jitter of the measured signal.The two measurement modes,multiplexed sampling and jitter processing,can implement multiple jitter type measurements without excessive hardware overhead.The high-precision jitter measurement circuit proposed in this thesis uses the SMIC 40 nm LL technology library to realize the front-end and back-end design of the measurement circuit.The presimulation verifies the correctness of the circuit function.Post-simulation analysis the influences of resolution,clock frequency,and jitter.The simulation results show that the average error of periodic jitter measurement is 2.81% and the average error of long-period jitter measurement is 3.67%.An area of 2448um2,power consumption of 0.37 mW,to meet the design needs.
Keywords/Search Tags:high precision, Edge alignment, Peried jitter, Long-period jitter, Interpolation sampler
PDF Full Text Request
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