Design Of A High-Speed Feed-Forward Equalizer And A Digital Phase Locked Loop In 0.18μm CMOS Technology

With the proposal and development of a series of new techniques including Big Data, Cloud Computing and Mobile Internet, it seems that the bandwidth of data communication system will never meet people’s requirement. As a result, high speed, high stability, low cost data communication system has been attracting more and more researchers’ attention.This paper first presents a 6.25Gb/s 3-tap T/2-spaced feed-forward equalizer (FFE), which can be used in 6.25Gb/s Serial data link. To meet the high speed requirement, a high frequency boost delay element using source capacitive degeneration is adopted. Additionally, a delay locked loop and a load calibration technique are used to overcome process variations. The proposed FFE is implemented in 0.18μm CMOS technology, and occupies an area of 0.67 ×0.74mm2. Test results show that the proposed FFE works properly at 6.25Gb/s and with a severely distorted signal, the FFE is able to restore its eye opening.Apart from the FFE, this paper also presents an all digital phase locked loop (ADPLL), which is aimed at 40GE and 100GE physical coding sublayer (PCS). Before the circuit design, a behavior model of the digital controlled oscillator and phase detector is built and the function of the ADPLL is verified via logic simulation. Then, the proposed ADPLL is implemented in 0.18μm CMOS technology and occupies an area of 0.44×0.44 mm2. Post-layout simulation results show that its output ranges from 476.7～962.4 MHz. The peak to peak jitter is less than 60ps@644.5MHz and the RMS jitter is less than 8.31ps@644.5MHz. The power dissipation is less than 9.2mW with a 1.8V power supply.Today, as the bandwidth of the data communication system continues to increase, the proposed FFE is of great value to the implementation of high speed serial data link receiver and the presented ADPLL is important to the ASIC design of 40GE and 100GE PCS.