Quantization Noise Reduction Technique For Delta-sigma Phase-locked Loop And Delay-locked Loop

As fundamental building blocks in wireline and wireless applications for signal generation and timing control respectively, the PLL (phase locked loop) and DLL (delay locked loop) have to meet critical specifications as the system is getting complex. TheΔΣmodulation technique becomes very popular nowadays. It provides more flexibility for PLL and DLL design by offering a high resolution. However, theΔΣPLL andΔΣDLL suffer from quantization noise, which will degrade the overall performance if it is not sufficiently suppressed. Focusing on applications such as clock generation, frequency synthesis and the timing control in high speed serial links, this dissertation has following achievements inΔΣPLL andΔΣDLL design with emphasis on quantization noise reduction techniques.The principle ofΔΣPLL andΔΣDLL is presented. The quantization noise issue is analyzed along with its relationship with the OSR (oversampling ratio) of the loop. The existing quantization noise reduction techniques are reviewed and the pros and cons of each technique are discussed. Besides, the design considerations for various applications are analyzed in both the system perspective and the circuit perspective. The design parameters ofΔΣmodulator are discussed and the benefits of using high-order single-loopΔΣmodulator are presented.A hybrid FIR noise filtering technique is proposed. Since it operates in discrete-time domain, the proposed technique is insensitive to analog mismatch, while it also improves the linearity with low hardware cost. Besides, it solves the noise amplification issue in existing digital FIR noise filtering technique by offering a unit DC gain.A 1GHzΔΣfractional-N PLL clock generator with the OSR as low as 13.5 is implemented in 0.18μm CMOS. The experimental results show that by employing the hybrid FIR noise filtering technique for overall quantization noise reduction, the short-term jitter of the fractional-N PLL clock generator can be reduced from 24.4mUIrms to 17.3mUIrms, which is comparable to 16.1mUIrms for integer-N PLL. A 2GHzΔΣfractional-N synthesizer for WCDMA/HSDPA application is implemented in 0.18μm RF CMOS. The phase-shifting scheme is adopted for the frequency divider so as to alleviate the power penalty. The experimental results prove that the hybrid FIR noise filtering technique can offer customized noise shaping according to the noise mask. It also makes the high-order single-loop modulator possible in low-order PLL for improving the integer-boundary spur performance.The concept of fractional-N likeΔΣDLL is proposed and a prototype 0.4-to-1.6 GHzΔΣDLL is implemented in 0.18μm CMOS. By employing frequency divider, blocks such as theΔΣmodulator, the phase multiplexer and the charge pump operate at a low frequency in the proposed topology. Therefore, it greatly alleviates the design effort and the power penalty of these blocks with glitch free operation. Since optional phases for modulation can be directly obtained at the divider output, it also takes away the necessity of multi-phase for the incoming clock of the DLL. The experimental results show that sub-ps resolution can be achieved based on low frequencyΔΣmodulation with the proposed topology.