The Analysis And Design Of All Digital Phase-Locked Loop Based On FPGA

Phase-Locked Loop is a negative feedback system that can effectively track the input signal's phase. With the development of digital integrated circuits, all digital phase-locked loop has also been rapid development. At the same time since the existence of the contradiction which is the locked time and the locked precision, the traditional Phase-Locked Loop is difficult to guarantee the locked accuracy to ensure the locked time. In view of this, some new structure all digital phase-locked loop are analyzed in this paper. All designs use the VHDL to program, and simulate with FPGA.Firstly, a new all digital phase-locked loop with PID control is proposed. The all digital phase-locked loop use the PID module to control the loop filter, in order to change the frequency coefficients of the VCO. PID control can effectively improve the locked precision, and the locked time is proportion to the frequency of the input signal. The structure of the VCO is simple, which can be seemed as a divider. The result of the simulation shows that the all digital phase-locked loop meets the goal of the expectation.Secondly, because traditional phase-locked loop appears continuous and same direction adjustment in order to decrease oscillation because of overshoot phase during capturing. A new all digital phase-locked loop with automatic modules control circuit is proposed. This system exploits the output of the phase detector to determine and switch the rapid capture, slow capture and the locked field. And by automatically control the mod of the loop filter to realize real-time control of the bandwidth and at the same time to avoid the all digital It can effectively overcome the conflict of the loop acquisition time and the noise of the loop, and accelerate the phase-locked speed and improve the performance of the loop. The simulation shows the effectiveness of the structure.Finally, from the consideration of the system power consumption, proposes a new all digital phase-locked loop with low-power and rapidly locked speed. This ADPLL uses an structure of odd and even counter which works at rising edge and falling edge. The loss of lock detection circuit according the state of lock to control the counter function of the loop filter, once the loop achieve locked state, the loop filter will stop counting. So it will reduce the frequency of the system's switching activity. The mod control module makes the signal of phase error as the enable signal of the module. As the loop reaches the locked state, the error will decrease, and the time of the control module is also greatly reduce, which to some extent reduces the power consumption. The experiment result shows that the structure can achieve the desire result.