Design Of Decimal Frequency Divider Based On Verilog-HDL

With the rapid development of integrated circuits, frequency synthesizer plays a very important role in the IC design. It is well-known that as a critical part of the frequency synthesizer, the fractional divider determines the performance of frequency synthesizer, include output accuracy, phase noise, lock time, and other important properties. So it is obvious that the design of a high-precision fractional divider is really necessary.It is presented that the digital circuit is a significant part of integrated circuit and the research status of frequency synthesizer is described, which through a lot of specific data. And emphatically introduces the current research situation of frequency synthesizer. The fractional divider is an important research direction in the study of digital circuit. Through the analysis of the current fractional divider circuit It have not yet found the fractional divider using digital circuit. Because of this, the paper proposed a fractional divider based on Dual-modulus fractional divider, which is realized by programmable digital circuit.This paper proposed a digital circuit implementation of programmable fractional frequency algorithm. It is analyzed that the existing algorithm of fractional divider, which is the parameters of successive approximation calculation. The cause of error is analyzed. The method is designed to control the error. An example is shown that the calculation process of frequency parameters.This paper presents the design and implementation of parameter calculation module and FPGA frequency module, Including floating-point adder, multiplier, integer divider module etc. the program using Verilog to realize.The simulation and prototype verification of the fractional divider is made, including the parameters calculation unit of fractional divider, the simulation of circuit and the FPGA prototype verification of fractional divider. The simulation and the test results of logic analyzer show that the circuit meets the design requirements. The error of the fractional divider can be controlled in less than 10E-9.