Σ-Δ Fractional-N Frequency Synthesizer For GPS

The recent development in the wireless communication industry has resulted inhigh demand for low-cost and high-performance RF frequency synthesizer whichgenerates many frequencies from one reference frequency. The most common frequencysynthesizer is an integer-N type, but the principle limitation of integer-N frequencysynthesizer has a problem that its frequency resolution is equal to the referencefrequency. Fractional-N approach eliminates this problem which exports fractionaldivision ratios using a multi-modulus divider controlled by a modulator. So thefractional-N frequency can achieve a small frequency resolution by using a largereference frequency. But it has an unwanted disadvantage of low frequency spur. Σ-Δnoise shaping technique can be used in the fractional-N frequency synthesizer for spursreduction.This paper studies the basic theory of the Σ-Δ technical and the structure of thePLL, then it is introduced how the spur can influence the phase noise. In this paper weintroduce two types of digital Σ-Δ modulator, MASH1-1-1and single stage withmultiple feedforward. The pros and cons of each topology are discussed in detail. Thenwe build up the model of these SDM in MATLAB. In such circumstance, the noiseshaping is researched in both of theory and simulation.At last, single stage Σ-Δ modulator and divider IP core is designed by using ASICdigital design flow. In the technical of TSMC0.18CMOS, the synthesis and layout ofthis design is finished. Through verification and back simulation this circuit meets therequirement of our target completely, the speed is10M, the noise shaping characteristicis nice.