Digital Back-end Design Of Power Line Carrier Chip

Power line as a modern social infrastructure, distributes widely. Power line carrier medium based smart meter has drawn more and more attention in the world. Power Line Carrier(PLC) chip is the core components of the smart meter. In this thesis, a kind of new power line carrier chip BES3803 with extended RF transceiver functions ability is studied. The main work is as follows:1. The logic synthesis of PLC chip with design for test(DFT) is performed by Design Compiler tool based on SMIC 0.18μm mixed signal process. In the logic synthesis, timing device in the PLC circuit is replaced with testable port device, and BIST circuit is inserted to memory device, so as to prepare for the chip test. Timing of gate-level netlist from logic synthesis is analyzed by Prime Time tool, and then formal verifications of RTL code and the gate-level netlist are conducted by Formality tool to guarantee correctness of logic synthesis.2. The physical layout of PLC chip is designed by Astro tool based on SMIC 0.18μm mixed signal process. The layout design includes placement, clock tree synthesis, routing, parasitic extraction, timing analysis, physical verification and formal verification. At the placement stage, a new optimization method of non-uniform ladder-type power mesh, which combines limiting module place and optimizing line width, is adopted to improve power mesh of the digital module, release chip winding space, reduce the chip area and optimize the chip power consumption. At the clock tree synthesis stage, a method of combining a local clock tree constructing and a new clock tree synthesis by ignoring gated clock skew check is adopted, the number of clock buffer insertion, the chip power and the chip area is reduced.3. The function, power loss and voltage drop of PLC chip are simulated. The results indicate that function of PLC chip is right. For chip expansion capabilities, a matching design is realized.In summary, a complete design work of the power line carrier chip BES3803 is performed from RTL(register-transfer level) to the GDSII(graphic design system II). The final chip area is 5.87mm2, the power is 61.116 mW and the test coverage is 98.21%. The chip shows a normal function and the performance, a great improvement in performance compared to the original chip. The chip has more powerful and stronger market competitiveness.