Design Of Rapidio Switch Chip’s Testbench Based On UVM

With the integrated circuit’s functions becoming more and more complicated, the verification effort has dominated the leading position in the design process and the traditional methodology has been unable to meet the verification requirements for modern design. So a new verification methodology is urgently needed. Universal Verification Methodology (UVM) is a new generation of the verification methodology which was launched by Cadence, Mentor and Synopsys in 2011. UVM inherited advantages of Verification Methodology Manual and Open Verification Methodology and overcame their shortcomings. It represented the development direction of Verification Methodology.In the paper, an overall design scheme of the UVM testbench was firstly made according to the structure and functions’characteristics of the RapidIO Switch Chip. In the scheme, one small Environment was designed for each high speed port, which only packaged one Input Agent and one Output Agent. And all of the small Environments shared one Reference Model and one Scoreboard. Finally, these small Environments, Reference Model and Scoreboard were packaged into one bigger Environment. Then, each component’s design of the testbench was implemented. For the Driver design, read request and read response operation were separated into two threads which were conventionally operated in the same one such that the technical problem was successfully solved that read request and read response signals of the Design under Test were completely independent. Generally, Scoreboard was designed under the idea of comparison in order. But the Scoreboard not only realized the out-of-order comparison but also had the comparison function in order. The two points were the technology highlight and innovation of this project research. As the verification results showed, its code coverage and the functional coverage respectively achieved 95.19% and 100.00%, which were fully satisfied the design demands.The practice proved that it had greatly shortened its verification cycle and improved its efficiency to make use of the UVM testbench to test the RapidIO Switch Chip functions. As the same time, it also provided the technical support for the follow-up project’s UVM testbench research of the internship company.