Design Of RapidIO Testbench Based On Communication SoC

As the expansion of mobile terminals and hardware computing ability,using embedded So C with rich resources and short development cycles has become the direction of design.At the same time,the promotion and application of technologies such as multi-core architecture and single-core upscaling are also in progress.The system bus frequency,delay and other indicators put forward high requirements.The RapidIO bus effectively solves the above problems as a pin-less,high-frequency,low-latency interconnect technology.How to efficiently verify and integrate RapidIO becomes the key to system interconnection.The complexity of the IP functions used in the current design is getting higher and higher,and more and more features are being used.It is particularly important to adopt appropriate verification methods to reasonably extract and verify the IP function points.However,general third-party vendors do not provide complete test cases,analyzers,and hardware simulation models for RapidIO independent verification environment.Therefore,researching on this technology can reduce the cost of secondary development and improve verification efficiency.Based on the above background research,this thesis proposes and designs a RapidIO verification platform based on the communication So C based on the analysis of the bus protocol.The verification scheme can effectively improve the efficiency of RapidIO verification,shorten the verification time,and ensure the hierarchical structure.The verification platform has certain reusability,maintainability and readability.The dissertation first analyzes the basic transmission protocol,port,function module partition,operation type,and packet format of RapidIO,and the signal and operation status of AMBA bus.Several common verification methods are briefly described,including the simulation verification method used in this paper.Based on the design of the verification platform,a complete software and hardware simulation test item is planned,including register and receive/send bidirectional IO logic and message transmission function verification,This scheme reasonably covers the function points of RapidIO and improves the accuracy and efficiency of verification.Second,build a complete simulation verification environment and FPGA verification environment.Including So C chip processing unit,interconnection bus,and storage unit selection,peripheral programming bus function model and data monitoring and analysis module.After completing the construction of the RapidIO verification platform,select the master node RapidIO to be attached to the bus,use the on-chip processing unit to send out the operation,input the test stimulus through the ARM bus interface,and use the peripheral bus model from the node RapidIO as the input stimulus to verify RapidIO receives the correctness of various operations as slaves.In the FPGA verification environment,select the appropriate board,replace the on-chip RAM and the high-speed interface integrated on the motherboard,and connect with the daughter board through a high-speed connection cable.In the real physical environment,locate problems through the Debug tool.The verification environment and functional model designed by this solution have certain reusability.Compared with the previous verification method using mirrored RapidIO,the flexibility and configurability are better.Finally,in a series of EDA tools such as Nc Verilog,CCS,and DS-5,a RapidIO maintenance operation,storage read/write operations,message operations,basic link training,and transmission performance at different speeds are cooperatively verified.Through verification and analysis,the So C and BFM models can cooperate with other peripheral units to normally cover the function points of RapidIO.The monitoring module can work normally and process operation information.Verification function coverage reaches 100%.The results show that the verification platform is reliable and the verified RapidIO IP function is normal.