The Study Of Bottom-up Functional Verification Approach Driven By Coverage Of Garfield

As a SOC, Garfield is of some typical characters. These characters bring many challenges and make functional verification a bottleneck of Garfield design. The difficulty of Garfield functional verification is as follows: setting up testbench; reusability of verification environment; coverage metrics;Setting up testbench mainly involves two problems: select the verification approach and choose the metrics of stimulus generation. The bottom-up approach is decided to be the verification approach by evaluating. The Garfield functional verification is divided to three levels: block level,subsystem level,whole chip level. At the whole chip level, we use platform based method. As to the generation of stimulus, experiments show that the constraint-random method is better than the traditional method completely.The reusability of the verification environment is very important. There are some defects in the earlier Garfield verification environment, such as: not separating reusable verification component; can not describe parallel streams of activity for each block; not keeping the description of components and activities at an abstract level; can not reuse between different levels. The paper modifies all these defects and makes the verification environment more reusable.Function coverage is the key component of Garfield functional verification. This paper deeply discusses the application of function coverage in Garfield verification. The method of setting up function coverage engineering model and two methods of analyzing coverage holes are discussed based on the function coverage mathematics model. Using the hole analysis method will improve coverage rapidly.It shows that many bugs are found by using the function verification project this paper discussed. MPW shows Garfield has met the design specification.