The Functional Simulation And Verification Of Application Specific Integrated Circuit

As large integrated circuits designs get more complex, functional verification is becoming the dominant task in the development process. Under this pressure, development teams are increasingly looking for new and innovative functional verification method. The thesis introduces an effective way to build a simulation-based automated verification platform to speed up the ASIC functional verification process. The simulation-based automated verification platform is made up with 5 modules: testbench, reference model, testcase, shell script and simulator. Testbench stimulates the RTL design and monitors its working status. Testbench is designed with a well-composed structure, which includes bus function models, verification elements, harness modules and test modules, so that each modules can be reusable. Reference model is written in C/C++ language and composed with stimulus data generator and hardware reference modules. Hardware reference modules implement the functions same as RTL model to proved the actual result that the RTL model should output. SystemC provides a fast way to build the hardware function reference module. Testcases are written in TCL language and can be read and parsed by the data generator in reference model. In UNIX system, a shell script integrates all the modules of the platform together, control the whole simulation process and provide a simple interface to verification engineers. A pre-simulation stage is designed to generate the test vector in the simulation process of the platform. We implement the simulation-based automated verification platform to verify the three ASIC chips that totally have 2M gates and 1M bits embedded ram in PMON project. The successful result of this case shows that this platform can meet the tight schedule of the project and guarantee to sign off the chips in one pass.