The Design And Verification Of RapidIO Switch Bus Functional Model

With the growing scale of integrated circuit design and continuous development of the design complexity, functions of products which have been designed are diversity. When it provides convenience to the users, it brings new challenges to the integrated circuits designers and manufacturers. In order to produce high-performance products in a lower design costs and shorter development cycles, it must be based on the accuracy and reliability of the design.Research shows that more than half of the chip productions need several rework and the main reason is the function error. So the importance of functional verification is self-evident. To solve the problem, we should not only make a breakthrough in technology, but also organize and use the resources in the field of the entire functional verification effectively. Verification Methodology should be studied in depth to find a right, appropriate and efficient method.Traditional functional verification method is only suitable for small scale integrated circuit development. With the increasing scale and complexity of IC design, traditional methods cannot meet the validation requirements. Bus functional model abstract and package the underlying signal, so that the test environment has a hierarchical structure features. It makes all authentication modules between different levels can be developed, at the same time it could improve the efficiency of verification. Meanwhile, in the verification of similar design, you can use the same bus functional model again and achieve the reusability of the bus functional model.In recent decades, the performance and the dominant frequency of the processor is improving continuously. So the transmission capacity of the processor bus becomes the bottleneck of technology development. Rapid IO is a new interconnect technology with a low latency, high bandwidth, high reliability, and it is widely used in embedded systems. The research object of this issue is the specific project I participated in during my internship. It is a switch chip based on Rapid IO interconnect protocol. The main work of this issue can be summarized as follows:Firstly, several common verification methods were compared and analyzed. According to the actual situation of the chip, considering the related allocation of resources, The simulation-based functional verification method was chosen to complete the verification work.Secondly, a detailed verification plan was developed based on the function test point ofthe DUT. Build a bus functional model as the testbench which meet the protocol specification and the functional requirements. To ensure the bus functional model can work correctly, it is necessary to verify its transmitting functional.Thirdly, the simulation result was analyzed. Configure the switch internal register through the bus functional model, select the authentication chip inside the core switching module functions to achieve the typical mode configuration, and apply the test stimulus to observe the output data packet and verify functional correctness and completeness.When the simulation result was analyzed, it is necessary to look at not only the contents of the packet but also their priority. So it is quite time-consuming to look at them one by one on the waveform. It is impossible to watch intuitively the order of the packets in the DUT. However, when a packet is sent out from the switch port to the interface of the bus functional model, the simulation process will generate some log files that is chronologically consecutive printed, which makes it possible to get the information about the contents and priorities of the packet all at once. This method greatly improves the efficiency of verification.