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Research On Key Technology Of Automatic Testbench Based On Muti-core SoC

Posted on:2013-12-10Degree:MasterType:Thesis
Country:ChinaCandidate:Y JiangFull Text:PDF
GTID:2248330395457089Subject:Integrated circuit system design
Abstract/Summary:PDF Full Text Request
With the development of integrated circuit manufacturing technology, theintegration of circuit is higher and higher, more function can be integrated in a singlechip, and the function of the system is becoming more and more complex, which makesthe verification much more difficult than before. Verification of VLSI is becomingbottleneck in the process of IC design. Many new verification methods are proposed,but there is still no breakthrough method to solve the problem. In this case, theverification engineers have to focus on how to verify the design better by the existingmethods.Network processor is a kind of application specific instruction processor facing thefield of network application, because of its complex structure and rich functionality,how to verify it become a difficult problem. In this thesis, the current mainstreamverification technique and methods are researched, and a kind of composite verificationmethod which integrates into object oriented programming technology,constrained-random stimulus generation, layered verification, assertion-basedverification and coverage-driven verification, and it can effectively improve theefficiency of verification. A testbench is designed and built in SystemVerilog based onthis method. This testbench provides a layered, controllable, observable and reusableverification environment for verification of the network processor. In the testbench,functional coverage is defined as the standard measure of verification progress. Themethod which uses to generate the test stimulus can be adjusted by observing thefunctional coverage, so that the stimulus will be as complete as possible and thefunctional coverage will convergence as soon as possible.In the thesis, the network processor is simulated by QuestaSim after the testbenchis built. The simulation result shows that all of the function points defined in the thesisare covered, and the code coverage has reached the intended target. It proves that thetestbench can meet the requirement of functional verification of the network processorbasically. At the same time, the performance of the network processor is analyzedthrough the data which collected by the testbench, its transmitting speed can achieve upto30MB/s.
Keywords/Search Tags:Network Processor, Functional Verification, SystemVerilog, Testbench, Functional Coverage
PDF Full Text Request
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