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Functional Testbench Design And Implementation Of AVS Video Decoder

Posted on:2012-05-07Degree:MasterType:Thesis
Country:ChinaCandidate:X G QiuFull Text:PDF
GTID:2218330338962888Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the development of integrated circuit technology, the market puts forward higher requirement about chips, they must be multifunction but more smaller,and have lower power consumption with the more reasonable price to gain a foothold in the fierce competition of market. Today IP reuse-based SoC has become the mainstream in chip design field, time-consuming SoC verification normally account for 70% of the entire design cycle, whose verification difficulties are 3 to 5 times of the traditional chip. So traditional verification methods can no longer meet current needs, verification has become one of the most challenging and valuable topics.Firstly,this paper discussed the position and the common methods of functional verification, analyzes the development trend of functional verification and applied them in practice.Then on the basis of the analysis of the AVS video decoder chip architecture and interfaces, an appropriative functional testbench was proposed. When it comes to the practical application of testbench, we analyzed the verification strategies of the entire chip and use the stimulus generation strategy-a combination of constraint-based random testing and directed testing, the coverage convergence strategy considering the code coverage and functional coverage, and the coverage-oriented verification flow with results back to the test side in the integrate verification. In order to improve the verification efficiency, the SystemVerilog-based reference modules replaced the modules whose designs were not complete yet, so that integrate verification could be activated in the case of uncompleted verification at the block level. Combined with the verification strategy the functional testbench showed its excellent performance, more verification efficiency and more code reuse compared to traditional testbench, thus the design cycle time was reduced. Finally, the paper carried out a brief summary of the entire work, and summarized the shortcomings and the main points of further work.
Keywords/Search Tags:System-on-Chip, Verification, SystemVerilog, Functional Testbench
PDF Full Text Request
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