The Verification Environment For IQ Stage In CIOQ Switch Fabric

With the rapid development of semiconductor technology, the scale of IC(Integrated Circuit) , including ASIC(Application Specific Integrated Circuit), SoC(System-On-a-Chip), IP(Intellectual Property) and so on, have greatly increased, and the logic on chip has become more and more complex, considering the requirement for low-cost and low-power in addition, the IC design has become more difficult. And then, the effort of verification will meet big challenge. The chip for network is one of the most complex ICs, and because of its high performance and urgent requirement of time-to-market, the verification engineers must provide a more effective and comprehensive method.Based on one type of PTN(Packet Transmission Network) chip, this thesis describes the verification environment for the Input-Switch-Memory and realization of various environmental modules concerning the function of CIOQ switching network on chip. Furthermore, the test method for the Input-Switch-Memory is illustrated as a step toward a effective and comprehensive solution for verification.Firstly, this thesis gives a introduction to Packet Switch technology based on the Queuing method, then introduces the structure of switching network on the chip and the structure of verification environment for the Input-Switch-Memory. Secondly, the following four chapters describe the content of the testbench and the concept on which it bases in order to describe the realization of the environment modules and how the concept of verification supports the design verification. This part provides some efficient ideas for the verification of successive chip designs with the similar function. These ideas would enhance the validity and effectiveness of chip verification.