Design Of Low Voltage Low Power PFD And CP

With the rapid developments of Low power wireless communication technology, Micro Electro Mechanism Systemand Embedded technology, Wireless sensor networks (WSN) emerge as the times require. It has been considered as one of the most important technologies of this century. Currently, WSN has been widely used in intelligent transportation, environmental monitoring, smart home, health care even military. It can be predicted that WSN will have profound impact to the human life in the near future, so the research and design for low power RF transceiver chip in WSN system has an important significance. As the key module of the WSN system low power consumption RF transceiver need more optimization and research. Phase frequency detector (PFD) and charge pump (CP) as the key module of the frequency synthesizer in low power RF transceiver, their performance affects the performance of RF transceiver.This paper has presented the design and realization of Phase Frequency Detector (PFD) and Charge Pump (CP) applied in WSN RF transceiver based on the analysis of basic concepts about Phase Locked Loop (PLL) synthesizer used in the wireless communication system. The PFD structure with TSPC (true single phase clocking) dynamic D flip-flop has been presented in this paper, which has low power cost, high speed and simple structure. Meanwhile, the optimization of PFD reset delay overcomes the dead-zone. Besides, a novel CP structure applying the low dropout current mirror is proposed. This design enlarges the output voltage region when the charge and discharge current matching. The rail to rail operational amplifier guarantees the high current matching precision as well. Moreover, the optimization of CP circuit overcome some non-ideal effect and the dynamic matching performance of CP charging and discharging current is improved. Then, the pre-simulation and post-simulation are taken based on the 0.18μm CMOS process with the supply voltage of IV. Post-simulation results show that the PFD&CP meet the design requirements and have good performance. The PFD has correct logic function and no dead-zone. With the supply voltage of 1V, under the three processes of SS, TT, FF, the CP direct current stable at 97μA-99μA and the current mismatching is less than 0.5μA with the output voltage range of 0.06V-0.95V. The logic function is correct in the cascade simulation of PFD&CP and the maximum power consumption is 236.2μW when the reference signal and frequency division signal have same frequency and phase under the three corner. The PED&CP meet the requirements of low power consumption.The PFD&CP of this design satisfy the application requirements of low power RF transceiver in WSN system, and can provide a reference for other RF transceiver frequency synthesizer design.