Design Of The Key Circuits Of Frequency Synthesizer For Wireless Communication

In recent years, RF front end has been hot as the fast development of wirelesscommunications. In a transmitting and receiving chip, frequency synthesizer provides aprogrammable carrier signal for the frequency conversion circuit of the transceiver, whichcan change the frequency of the output-signal of frequency synthesizer in order to realizethe channel switching under the control of the programmable output-signal at any time andis a core module of a transceiver. The work of this thesis is design of the key circuits offrequency synthesizer.This thesis discuss the definitions and the working principles of frequency synthesizerand PLL.It also analyze the phase detector’s performance index, PFD’s dead zone effect.The PFD includes two D flip-flops with three inverters in front of them to ensure enoughworking time of the two D flip-flops, thus eliminating the dead zone effect.Charge pump’s non ideal effect is studied.The mismatch between current source andcurrent sink and the charge sharing make the output rippling. A structure of charge pump toavoid the charge sharing is adopted.VCO subsystem is the main module and generate two pure orthogonal signal totransmitting mixer and receiving mixer. AC coupling, which follows the principle ofisolating the common mode voltage, is adopted to solve the VCO and VCO buffer’scoupling problem. The subsystem’s output frequency range is1.59~1.67GHz，the peak topeak of the output is1.2V，phase noise is-118dBc/Hz1.6GHz@1MHz offset. It worksunder the voltage of2.5V and current consumption is6~7mA.Dual-mode prescaler structure is used in the programmable divider to realize thefrequency’s divide-by-15or divide-by-16function when mode-control signal16is0or1.