Design Of PFD And CP Used In Phase-Locked Loop Of Radio Frequency

With the development of digital communication system, wireless digital audio technology has gradually become the third generation of broadcasting technology. At the same time, people need CD quality audio and more multimedia, also for L-band wireless communication applications, while RF transceiver is the key module for wireless system. Because of the advantages of the CMOS process technology, with its low cost and the static power consumption, achieving high speed RF transceiver integrated circuit with the process has become the trend of development. In the RF receiver architecture, the phase-locked loop (PLL) frequency synthesizer providing the local oscillator signal becomes an integral part of the circuit, which determines the quality of the received signal and as key modules of PLL, the phase-and-frequency detector (PFD) provides frequency resolution, while the charge pump (CP) ensures a wide acquisition range.The PFD and CP circuits are designed with the requirements of the PLL for L-band multimode wireless communication and wireless digital broadcast communication in this paper. Firstly, the system’s parameters are designed with three-order loop filter according to the requirements of the L-band wireless communication system,whose loop bandwidth is 100-200kHz, the phase margin is greater than 50°, and the lock-time is less than 40 s, Subsequently, on the bases of TSPC-D flip-flop, the proposed linear PFD circuit, which has the advantages of simple structure, good symmetry and compromises the dead and blind range of phase with delay cells, is presented, and according to the CP’s requirements, a high-speed current-steering switching CP is raised, whose current range is 100～400μA with four channels in order to stabilize the loop bandwidth by fitting the VCO’s gain. In the next section, a high-flatness of current CP is proposed with the double clamped amplifier for the wireless digital radio communication system, where a unit-gain amplifier, the current compensation circuit and some other auxiliary modules are joined to make the CP with good properties. Finally, based on a 0.18-μm CMOS process, the PFD and CP for the wireless digital radio communication are fabricated and tested. Measurement results show that the PFD has a correct logic function with a 1.8-V supply voltage and its detection range is [-1.90π,1.90π] without dead zone, and the CP current is 48.3 μA. The current mismatch and variation are less than 1% and 2% at output voltage range of 0.3～1.6 V, with total power consumption of 1.8～2.8 mW.As a new hotspot in the wireless communication, the design of PFD and CP used in wireless digital broadcast and L-band multimode wireless communication receiver has not only engineering application value but also prospect of broad market application.