Research On Key Technologies Of Low Power Phase Locked Loop Frequency Synthesizer

As a core module and major energy-consuming module in modern electronic communication systems,it is necessary to study the design of low-power frequency synthesizers.Among the current mainstream frequency synthesizer implementation methods,phase-locked loops are widely used and a research focus.Therefore,designing low-power phase-locked loops is crucial.The current mainstream phase-locked loop structure is a charge pump phase-locked loop,which includes analog and digital circuit modules and is a mixed-signal negative feedback system.For such a complex integrated system,researching the overall architecture of the system and carefully selecting system parameters is the first step in design.This article first analyzes the system theory of phase-locked loops,clarifies the working principles of phase-locked loop systems and various modules,introduces the design process and noise theory of phase-locked loops,focuses on analyzing the relationship between noise and power consumption of phase-locked loops,and analyzes each module’s design details.Based on the above research analysis,a charge pump phase-locked loop was designed.According to the design process and methods described in this article,according to the system indicators of phase-locked loops calculated specific indicator requirements for each submodule.On 55 nm CMOS RF technology using Cadence Spectre design platform completed circuit design simulation work.After completing schematic design simulation use Cadence Virtuoso platform completed layout design post-simulation.The simulation results show that under a 1.2V supply voltage,the overall power consumption of the phase-locked loop circuit is 3.6mW,the input reference frequency is20 MHz,and the locking time is less than 20 μs.When the phase-locked loop is locked at the 1GHz output frequency,the phase noise is-116 d Bc/ Hz@1MHz,with a chip area of820μm×580μm.